US 11,749,365 B2
Semiconductor device
Masayuki Sakakura, Isehara (JP); Yuugo Goto, Isehara (JP); Hiroyuki Miyake, Atsugi (JP); and Daisuke Kurosaki, Tochigi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Sep. 21, 2021, as Appl. No. 17/480,311.
Application 17/480,311 is a continuation of application No. 16/780,027, filed on Feb. 3, 2020, granted, now 11,133,078.
Application 16/780,027 is a continuation of application No. 16/547,976, filed on Aug. 22, 2019, granted, now 10,580,508, issued on Mar. 3, 2020.
Application 16/547,976 is a continuation of application No. 16/017,181, filed on Jun. 25, 2018, granted, now 10,431,318, issued on Oct. 1, 2019.
Application 16/017,181 is a continuation of application No. 13/632,564, filed on Oct. 1, 2012, granted, now 10,014,068, issued on Jul. 3, 2018.
Claims priority of application No. 2011-222990 (JP), filed on Oct. 7, 2011.
Prior Publication US 2022/0005536 A1, Jan. 6, 2022
Int. Cl. G11C 19/18 (2006.01); H01L 27/12 (2006.01); H01L 27/02 (2006.01)
CPC G11C 19/184 (2013.01) [H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0286 (2013.01); H01L 27/0248 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
first to tenth transistors having a same channel type,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, and the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring, and the other of the source and the drain of the second transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring, and the other of the source and the drain of the third transistor is electrically connected to a gate of the seventh transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the seventh transistor, and the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to the fourth wiring, and the other of the source and the drain of the fifth transistor is electrically connected to a gate of the first transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the fourth wiring, the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, and a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the eighth transistor is electrically connected to the fourth wiring, the other of the source and the drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor, and a gate of the eighth transistor is electrically connected to the gate of the first transistor,
wherein the other of the source and the drain of the ninth transistor is electrically connected to a sixth wiring,
wherein one of a source and a drain of the tenth transistor is electrically connected to the gate of the first transistor,
wherein a first conductive layer serving as the gate of the first transistor is electrically connected to a third conductive layer serving as a gate of the third transistor through a second conductive layer, and
wherein the second wiring is configured to transmit a signal output from a circuit including the first to tenth transistors.