US 11,749,361 B2
Memory device and operating method thereof
Young Il Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 7, 2022, as Appl. No. 17/859,795.
Application 17/859,795 is a continuation of application No. 17/220,453, filed on Apr. 1, 2021, granted, now 11,456,041.
Claims priority of application No. 10-2020-0136192 (KR), filed on Oct. 20, 2020.
Prior Publication US 2022/0351791 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell coupled to a bit line and a word line;
a page buffer coupled to the bit line, and configured to output a bit line voltage to the bit line in response to a page buffer sensing signal; and
control logic configured to:
output, to the page buffer, a signal increased from a first voltage level at a first time of a precharge period to a second voltage level at a second time of the precharge period, as the page buffer sensing signal,
in response to the second voltage level being less than a target voltage level, output, to the page buffer, a pulse signal having the target voltage level at a third time of the precharge period, as the page buffer sensing signal, and
output a control signal to provide a program voltage to the word line after the precharge period.