CPC G11C 16/08 (2013.01) [G11C 11/4074 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01)] | 9 Claims |
1. A memory device comprising:
a memory block including a plurality of memory cells connected to word lines;
peripheral circuits configured to generate operation voltages to be applied to the word lines; and
control logic configured to control the peripheral circuits in response to a program command, a read command, or an erase command,
wherein the peripheral circuits are configured such that each level of threshold voltages of a lowest programmed state and a highest programmed state is changed according to a distance between the word lines.
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