US 11,749,345 B2
Memory device and method of operating memory device
Sang Heon Lee, Chungcheongbuk-do (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Aug. 3, 2021, as Appl. No. 17/393,027.
Application 17/393,027 is a continuation of application No. 16/707,300, filed on Dec. 9, 2019, granted, now 11,107,532.
Claims priority of application No. 10-2019-0075458 (KR), filed on Jun. 25, 2019.
Prior Publication US 2021/0366548 A1, Nov. 25, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 11/4074 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 16/12 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 11/4074 (2013.01); G11C 16/12 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory block including a plurality of memory cells connected to word lines;
peripheral circuits configured to generate operation voltages to be applied to the word lines; and
control logic configured to control the peripheral circuits in response to a program command, a read command, or an erase command,
wherein the peripheral circuits are configured such that each level of threshold voltages of a lowest programmed state and a highest programmed state is changed according to a distance between the word lines.