CPC G11C 16/0466 (2013.01) [G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/0416 (2013.01); G11C 16/0483 (2013.01); G11C 16/0491 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/28 (2013.01); G11C 16/3427 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/32133 (2013.01); H01L 21/76892 (2013.01); H01L 23/528 (2013.01); H01L 27/0688 (2013.01); H01L 28/00 (2013.01); H01L 29/04 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/16 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/6675 (2013.01); H01L 29/66833 (2013.01); H01L 29/78642 (2013.01); H01L 29/7926 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 31 Claims |
1. A process for creating a memory structure over a planar surface of a semiconductor substrate, comprising:
depositing a first insulation layer over the planar surface;
over the first insulation layer, forming a plurality of material layers each separated from another by an intervening insulator layer, each material layer comprising either a conductive material or a sacrificial material;
etching a plurality of trenches through the material layers and the intervening insulator layers until reaching the planar surface, each trench extending in depth along a first direction substantially normal to the planar surface;
conformally depositing a charge-trapping layer over the sidewalls of the trenches;
conformally depositing a lightly doped polysilicon of a first conductivity over the surface of the charge-trapping layers on the sidewalls of the trenches;
filling the trenches with a dielectric material; and
forming in each filled trench first and second shafts, each shaft having the lightly doped polysilicon as a portion of its sidewalls; and
filling each shaft with a heavily doped polysilicon material of a second conductivity opposite the first conductivity.
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