CPC G11C 13/004 (2013.01) [G06F 9/5016 (2013.01); G06N 3/063 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0069 (2013.01); G11C 29/006 (2013.01); G11C 29/26 (2013.01); G11C 2029/4402 (2013.01); G11C 2211/561 (2013.01)] | 27 Claims |
1. A device, comprising:
a memory having a memory array organized as a plurality of rows intersecting a plurality of columns, wherein, in operation, memory cells of a cut of the memory array store information indicative of reliability types of regions of the memory, including information indicative of reliability types of regions of the memory array; and
control circuitry coupled to the memory, wherein the control circuitry, in operation, responds to a request to allocate memory to a process sharing the memory by:
determining a request type associated with the request to allocate memory; and
allocating memory to the process based on the request type associated with the request to allocate memory and the stored information indicative of reliability-types stored in the cut of the memory array.
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