CPC G11C 11/4091 (2013.01) [G06F 15/7821 (2013.01); G11C 7/1006 (2013.01); G11C 11/4087 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] | 18 Claims |
1. A memory device comprising:
a memory cell array including a plurality of memory cells; and
a processor-in-memory (PIM) configured to perform an internal processing operation in response to an internal processing operation command,
wherein, in a normal mode, the memory device is configured to perform a data transaction operation between a memory controller and the memory cell array,
wherein, in an internal processing mode, the PIM determines a first command indicating a type of the internal processing operation, transmits the first command to the memory controller, and receives a second command related to the first command from the memory controller, the second command being the internal processing operation command.
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