US 11,749,337 B2
Memory device adjusting duty cycle and memory system having the same
Dae-Sik Moon, Suwon-si (KR); Gil-Hoon Cha, Hwaseong-si (KR); Ki-Seok Oh, Seoul (KR); Chang-Kyo Lee, Seoul (KR); Yeon-Kyu Choi, Seoul (KR); Jung-Hwan Choi, Hwaseong-si (KR); Kyung-Soo Ha, Hwaseong-si (KR); and Seok-Hun Hyun, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 16, 2022, as Appl. No. 17/807,163.
Application 17/807,163 is a continuation of application No. 17/564,564, filed on Dec. 29, 2021, granted, now 11,423,971.
Application 17/564,564 is a continuation of application No. 17/148,915, filed on Jan. 14, 2021, granted, now 11,393,522.
Application 17/148,915 is a continuation of application No. 16/230,185, filed on Dec. 21, 2018, granted, now 10,923,175, issued on Feb. 16, 2021.
Claims priority of application No. 10-2018-0012423 (KR), filed on Jan. 31, 2018; and application No. 10-2018-0062094 (KR), filed on May 30, 2018.
Prior Publication US 2022/0310151 A1, Sep. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/40 (2006.01); G11C 11/4076 (2006.01); G11C 11/409 (2006.01); G06F 3/06 (2006.01); G11C 7/22 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 7/222 (2013.01); G11C 11/409 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for performing a duty adjustment operation in a memory system, the method comprising:
performing a first duty adjustment operation on a write clock, the first duty adjustment operation including:
transmitting, by a memory controller, the write clock to a synchronous dynamic random access memory (SDRAM) device;
performing a first duty monitoring operation on the write clock to generate a first duty monitoring information and transmitting the first duty monitoring information to the memory controller; and
adjusting a duty cycle of the write clock based on the first duty monitoring information; and
performing a second duty adjustment operation on a read clock, the second duty adjustment operation including:
generating, by the SDRAM device, the read clock based on the write clock and transmitting the read clock to the memory controller;
performing a second duty monitoring operation on the read clock to generate a second duty monitoring information and transmitting the second duty monitoring information to the memory controller; and
adjusting a duty cycle of the read clock based on the second duty monitoring information.