CPC G11C 11/40622 (2013.01) [G06F 12/0811 (2013.01); G06F 12/1433 (2013.01); G11C 11/40615 (2013.01); G11C 29/42 (2013.01); G11C 29/4401 (2013.01)] | 13 Claims |
1. A memory system, comprising:
a normal memory area suitable for storing normal data;
a security memory area suitable for storing security data;
a first row hammering detection circuit suitable for sampling a portion of rows that are activated in the normal memory area and counting activation numbers of the sampled rows to select first rows to be refreshed among the sampled rows; and
a second row hammering detection circuit suitable for counting activation numbers of all rows in the security memory area to select second rows to be refreshed.
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