US 11,749,332 B2
Effective DRAM interleaving for asymmetric size channels or ranks while supporting improved partial array self-refresh
Kunal Desai, Bangalore (IN); Saurabh Jaiswal, Kaushambi (IN); Vikrant Kumar, Bangalore (IN); Swaraj Sha, Bangalore (IN); and Dharmesh Parikh, Bangalore (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 11, 2021, as Appl. No. 17/174,073.
Prior Publication US 2022/0254409 A1, Aug. 11, 2022
Int. Cl. G11C 29/00 (2006.01); G11C 11/406 (2006.01); G06F 12/06 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01)
CPC G11C 11/40618 (2013.01) [G06F 12/0607 (2013.01); G11C 11/408 (2013.01); G11C 11/4093 (2013.01); G11C 11/40615 (2013.01); G06F 12/06 (2013.01)] 40 Claims
OG exemplary drawing
 
1. A method of portion interleaving for asymmetric size memory portions of a memory, comprising:
determining an asymmetric memory portion assignment for a first interleave unit, wherein the asymmetric memory portion assignment is to a first asymmetric memory portion;
determining a consumed address space offset for consumed address space of the memory;
modifying an address of the first interleave unit using the consumed address space offset; and
assigning the first interleave unit to a first interleave granule in the first asymmetric memory portion using the modified address in a compact manner such that the first interleave unit is assigned to the first interleave granule while the first interleave granule has unused space before mapping another interleave unit to another interleave granule.