US 11,749,330 B2
Charge leakage detection for memory system reliability
Angelo Visconti, Appiano Gentile (IT); Riccardo Pazzocco, Verona (IT); Jonathan J. Strand, Boise, ID (US); and Kevin T. Majerus, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 7, 2022, as Appl. No. 18/53,305.
Application 18/053,305 is a continuation of application No. 16/831,524, filed on Mar. 26, 2020, granted, now 11,514,968.
Prior Publication US 2023/0114735 A1, Apr. 13, 2023
Int. Cl. G11C 11/22 (2006.01); G11C 29/50 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 11/221 (2013.01); G11C 11/2259 (2013.01); G11C 11/2275 (2013.01); G11C 29/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array; and
circuitry coupled with the memory array and configured to:
perform a leakage detection evaluation of the memory array, wherein, to perform the leakage detection evaluation, the circuitry is configured to:
establish a diagnostic condition of a memory cell of the memory array; and
determine a leakage condition of the memory array, after establishing the diagnostic condition of the memory cell, based at least in part on evaluating an electrical characteristic of an access line coupled with the memory cell; and
initiate a recovery operation based at least in part on the determined leakage condition of the memory array.