US 11,749,326 B2
Dynamic random access memory (DRAM) device and memory controller therefor
Seung-Jun Shin, Incheon (KR); and Tae-Young Oh, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 12, 2022, as Appl. No. 17/862,718.
Application 17/862,718 is a continuation of application No. 17/387,036, filed on Jul. 28, 2021.
Application 17/387,036 is a continuation of application No. 16/874,916, filed on May 15, 2020, granted, now 11,081,152, issued on Aug. 3, 2021.
Application 16/874,916 is a continuation of application No. 16/717,742, filed on Dec. 17, 2019, granted, now 10,930,330, issued on Feb. 23, 2021.
Application 16/717,742 is a continuation of application No. 16/169,178, filed on Oct. 24, 2018, granted, now 10,579,263, issued on Mar. 3, 2020.
Application 16/169,178 is a continuation of application No. 15/690,379, filed on Aug. 30, 2017, granted, now 10,114,548, issued on Oct. 30, 2018.
Application 15/690,379 is a continuation of application No. 15/180,175, filed on Jun. 13, 2016, granted, now 9,754,649, issued on Sep. 5, 2017.
Claims priority of application No. 10-2015-0126786 (KR), filed on Sep. 8, 2015.
Prior Publication US 2022/0351764 A1, Nov. 3, 2022
Int. Cl. G11C 8/06 (2006.01); G11C 8/18 (2006.01); G11C 8/10 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G11C 8/06 (2013.01) [G06F 3/06 (2013.01); G06F 13/1689 (2013.01); G11C 7/10 (2013.01); G11C 7/1045 (2013.01); G11C 7/22 (2013.01); G11C 8/10 (2013.01); G11C 8/18 (2013.01); G11C 11/4076 (2013.01); G11C 7/1057 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM) device operating in synchronization with a clock signal, the DRAM device comprising:
a memory cell array including a plurality of memory cells; and
a control logic configured to receive a command which is split into a first portion and a second portion, the first portion of the command including a first portion of an address and the second portion of the command including a second portion of the address, the first portion and the second portion of the address, combined together, indicating a location of memory cells operating in response to the command,
wherein the control logic, during a first operating mode, receives the first portion of the command and the second portion of the command at first and second rising edges of the clock signal respectively in which the second rising edge follows the first rising edge after a first number of clock cycles, and during a second operating mode, receives the first portion of the command and the second portion of the command at third and fourth rising edges of the clock signal respectively in which the fourth rising edge follows the third rising edge after a second number of clock cycles, and the first number and the second number are different from each other.