CPC G11C 7/1063 (2013.01) [G11C 7/1039 (2013.01); G11C 7/1042 (2013.01); G11C 7/1069 (2013.01); G11C 8/18 (2013.01)] | 18 Claims |
1. An integrated circuit (IC) chip, comprising:
a plurality of interlayer channels;
at least one data pad;
an identification (ID) generation circuit suitable for generating a chip ID signal by decoding a command/address signal;
a first transmission circuit suitable for transferring a plurality of internal data pieces to a transmission path by aligning a plurality of interlayer data pieces respectively transferred from the plurality of interlayer channels according to a plurality of strobe signals while selectively inverting the plurality of interlayer data pieces according to the chip ID signal; and
a second transmission circuit suitable for transferring the plurality of internal data pieces from the transmission path to the at least one data pad.
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