US 11,749,318 B2
Interface protocol configuration for memory
Richard C. Murphy, Boise, ID (US); Glen E. Hush, Boise, ID (US); and Honglin Sun, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 15, 2022, as Appl. No. 17/888,457.
Application 17/888,457 is a division of application No. 16/811,361, filed on Mar. 6, 2020, granted, now 11,417,372.
Prior Publication US 2022/0392499 A1, Dec. 8, 2022
Int. Cl. G11C 7/10 (2006.01); G06F 13/38 (2006.01); G06F 9/30 (2018.01); G06F 9/54 (2006.01)
CPC G11C 7/1045 (2013.01) [G06F 9/30189 (2013.01); G06F 9/30196 (2013.01); G06F 9/546 (2013.01); G06F 13/387 (2013.01); G11C 7/1039 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing apparatus, comprising:
a memory device;
a processing resource coupled to the memory device and configured to:
provide a first command to the memory device wherein the first command is compliant with a first standardized interface protocol of the memory device;
provide a second command to the memory device to set a mode register of the memory device;
provide a third command to the memory device wherein the third command is not compliant with the first interface protocol of the memory device; and
provide a fourth command to the memory device to reset the mode register.