US 11,749,161 B2
Gate driving circuit and driving method thereof and display panel
Yingmeng Miao, Beijing (CN); Changcheng Liu, Beijing (CN); Zhihua Sun, Beijing (CN); Yanping Liao, Beijing (CN); Seungmin Lee, Beijing (CN); Xibin Shao, Beijing (CN); Cong Wang, Beijing (CN); and Feng Qu, Beijing (CN)
Assigned to Beijing Boe Display Technology Co., Ltd., Beijing (CN); and Boe Technology Group Co., Ltd., Beijing (CN)
Filed by BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., Beijing (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Dec. 16, 2022, as Appl. No. 18/82,691.
Application 18/082,691 is a continuation of application No. 17/351,638, filed on Jun. 18, 2021, granted, now 11,568,778.
Claims priority of application No. 202011068583.3 (CN), filed on Sep. 30, 2020.
Prior Publication US 2023/0196961 A1, Jun. 22, 2023
Int. Cl. G09G 3/20 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/20 (2013.01) [G11C 19/28 (2013.01); G09G 2300/0408 (2013.01); G09G 2300/08 (2013.01); G09G 2310/0243 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A gate driving circuit comprising multiple stages of shift registers, the multiple stages of shift registers comprising N first shift registers arranged alternately with N second shift registers,
wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals;
wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals;
wherein K and N are both integers greater than 1, and K<N;
wherein an input signal terminal of an n-th stage of first shift register in the N stages of first shift registers is coupled to an output signal terminal of an (n−i)-th stage of first shift register in the N stages of first shift registers, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register in the N stages of first shift registers;
wherein an input signal terminal of an n-th stage of second shift register in the N stages of second shift registers is coupled to an output signal terminal of an (n−i)-th stage of second shift register in the N stages of second shift registers, and a reset signal terminal of the n-th stage of second shift register is coupled to an output signal terminal of an (n+j)-th stage of second shift register in the N stages of second shift registers;
wherein n, i, and j are all integers greater than 0, K is an even number, 1<n<N, 1≤i≤K/2, and K/2+1≤j≤K−1; and
wherein K=6, i=3, and j=4.