US 11,748,841 B2
Coordination and increased utilization of graphics processors during inference
Abhishek R. Appu, El Dorado Hills, CA (US); Altug Koker, El Dorado Hills, CA (US); John C. Weast, Portland, OR (US); Mike B. Macpherson, Portland, OR (US); Linda L. Hurd, Cool, CA (US); Sara S. Baghsorkhi, San Jose, CA (US); Justin E. Gottschlich, Santa Clara, CA (US); Prasoonkumar Surti, Folsom, CA (US); Chandrasekaran Sakthivel, Sunnyvale, CA (US); Liwei Ma, Beijing (CN); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Kamal Sinha, Cordova, CA (US); Joydeep Ray, Folsom, CA (US); Balaji Vembu, Folsom, CA (US); Sanjeev Jahagirdar, Folsom, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); and Dukhwan Kim, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 22, 2022, as Appl. No. 17/871,781.
Application 17/871,781 is a continuation of application No. 17/143,805, filed on Jan. 7, 2021, granted, now 11,430,082.
Application 17/143,805 is a continuation of application No. 16/377,315, filed on Apr. 8, 2019, granted, now 10,891,707, issued on Jan. 12, 2021.
Application 16/377,315 is a continuation of application No. 15/495,054, filed on Apr. 24, 2017, granted, now 10,304,154, issued on May 28, 2019.
Prior Publication US 2022/0366527 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06T 1/20 (2006.01); G06N 3/063 (2023.01); G06F 9/46 (2006.01); G06N 3/045 (2023.01); G06N 3/08 (2023.01); G06N 3/084 (2023.01); G06N 3/044 (2023.01)
CPC G06T 1/20 (2013.01) [G06F 9/46 (2013.01); G06N 3/045 (2023.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G06N 3/044 (2023.01); G06N 3/084 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a processing system including a graphics processor, the graphics processor including a plurality of processing resources, the plurality of processing resources configured to be partitioned into a plurality of physical resource slices, wherein the processing system has a capability to limit usage of the plurality of processing resources by a plurality of contexts, the graphics processor includes a plurality of memory partitions, the plurality of physical resource slices includes a plurality of compute resource partitions, and the plurality of compute resource partitions is associated with a plurality of memory access paths to the plurality of memory partitions; and
circuitry configured to:
receive specification of a limitation on usage of the plurality of processing resources by respective contexts of the plurality of contexts;
schedule workloads associated with the plurality of contexts to the plurality of physical resource slices according to the limitation on usage specified for the respective contexts of the plurality of contexts;
limit execution of workloads for respective contexts of the plurality of contexts to a specified subset of the plurality of processing resources according to the physical resource slices associated with the respective contexts of the plurality of contexts; and
monitor, during execution of a workload associated with a context of the plurality of contexts, a utilization percentage of the specified subset of the plurality of processing resources to which the context is limited.