US 11,748,606 B2
Dynamic precision for neural network compute operations
Kamal Sinha, Rancho Cordova, CA (US); Balaji Vembu, Folsom, CA (US); Eriko Nurvitadhi, Hillsboro, OR (US); Nicolas C. Galoppo Von Borries, Portland, OR (US); Rajkishore Barik, Santa Clara, CA (US); Tsung-Han Lin, Campbell, CA (US); Joydeep Ray, Folsom, CA (US); Ping T. Tang, Edison, NJ (US); Michael S. Strickland, Sunnyvale, CA (US); Xiaoming Chen, Shanghai (CN); Anbang Yao, Beijing (CN); Tatiana Shpeisman, Menlo Park, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Altug Koker, El Dorado Hills, CA (US); Farshad Akhbari, Chandler, AZ (US); Narayan Srinivasa, Portland, OR (US); Feng Chen, Shanghai (CN); Dukhwan Kim, San Jose, CA (US); Nadathur Rajagopalan Satish, Santa Clara, CA (US); John C. Weast, Portland, OR (US); Mike B. MacPherson, Portland, OR (US); Linda L. Hurd, Cool, CA (US); Vasanth Ranganathan, El Dorado Hills, CA (US); and Sanjeev S. Jahagirdar, Folsom, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on May 11, 2021, as Appl. No. 17/317,857.
Application 17/317,857 is a continuation of application No. 15/495,020, filed on Apr. 24, 2017, granted, now 11,010,659.
Prior Publication US 2021/0334637 A1, Oct. 28, 2021
Int. Cl. G06F 7/50 (2006.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G06N 3/04 (2023.01); G06T 1/20 (2006.01); G06F 9/30 (2018.01); G06T 15/00 (2011.01); G06F 15/78 (2006.01); G06F 15/76 (2006.01); G06F 1/3287 (2019.01); G06F 1/3293 (2019.01); G06N 3/084 (2023.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06T 1/60 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 1/3287 (2013.01); G06F 1/3293 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 15/76 (2013.01); G06F 15/78 (2013.01); G06N 3/04 (2013.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01); G06T 1/60 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one processing resource;
at least one field programmable gate array (FPGA) communicatively coupled to the at least one processing resource; and
a processor to:
determine one or more workload requirements for at least one of a workload or an execution thread;
remap the at least one of the workload or the execution thread to the FPGA on a selective basis; and
convert the low compute load operations into bits which become part of a context state of a thread.