CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01)] | 20 Claims |
1. An integrated circuit chip device, comprising:
a main processing circuit; and
a plurality of basic processing circuits;
wherein:
the plurality of basic processing circuits are arranged as an array having h rows and w columns, each basic processing circuit is connected to an adjacent basic processing circuit, the main processing circuit is connected to w basic processing circuits in a first row, w basic processing circuits in an hth row, and h basic processing circuits in a first column;
the main processing circuit is configured to:
perform respective neural network computations in series; and
transfer data to the basic processing circuits that are connected to the main processing circuit;
at least one of the plurality of basic processing circuits is configured to:
perform computations in the neural network in parallel according to the transferred data; and
transfer computation results to the main processing circuit through the basic processing circuits that are connected to the main processing circuit.
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