US 11,748,605 B2
Integrated circuit chip device
Shaoli Liu, Beijing (CN); Xinkai Song, Beijing (CN); Bingrui Wang, Beijing (CN); Yao Zhang, Beijing (CN); and Shuai Hu, Beijing (CN)
Assigned to CAMBRICON TECHNOLOGIES CORPORATION LIMITED, Beijing (CN)
Filed by CAMBRICON TECHNOLOGIES CORPORATION LIMITED, Beijing (CN)
Filed on Dec. 27, 2020, as Appl. No. 17/134,487.
Application 17/134,487 is a continuation of application No. 16/903,304, filed on Jun. 16, 2020, granted, now 11,544,546.
Application 16/903,304 is a continuation of application No. PCT/CN2018/123929, filed on Dec. 26, 2018.
Claims priority of application No. 201711455388.4 (CN), filed on Dec. 27, 2017; application No. 201711455397.3 (CN), filed on Dec. 27, 2017; application No. 201711466943.3 (CN), filed on Dec. 28, 2017; application No. 201711468629.9 (CN), filed on Dec. 28, 2017; application No. 201711469408.3 (CN), filed on Dec. 28, 2017; application No. 201711469614.4 (CN), filed on Dec. 28, 2017; and application No. 201711469615.9 (CN), filed on Dec. 28, 2017.
Prior Publication US 2021/0117767 A1, Apr. 22, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); G06N 3/04 (2023.01)
CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit chip device, comprising:
a main processing circuit; and
a plurality of basic processing circuits;
wherein:
the plurality of basic processing circuits are arranged as an array having h rows and w columns, each basic processing circuit is connected to an adjacent basic processing circuit, the main processing circuit is connected to w basic processing circuits in a first row, w basic processing circuits in an hth row, and h basic processing circuits in a first column;
the main processing circuit is configured to:
perform respective neural network computations in series; and
transfer data to the basic processing circuits that are connected to the main processing circuit;
at least one of the plurality of basic processing circuits is configured to:
perform computations in the neural network in parallel according to the transferred data; and
transfer computation results to the main processing circuit through the basic processing circuits that are connected to the main processing circuit.