CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01)] | 20 Claims |
1. An integrated circuit chip device configured to perform neural network forward computations, wherein the neural network has n layers, the integrated circuit chip device comprising:
a main processing circuit; and
a plurality of basic processing circuits,
wherein:
the main processing circuit comprises a data type conversion circuit configured to convert data between a floating point data type and a fixed point data type;
the main processing circuit is configured to:
receive a first operation instruction;
parse the first operation instruction to obtain a first computation instruction included in an ith layer of the forward computations of the first operation instruction and corresponding input data and weight data of the first operation instruction, wherein:
i is an integer greater than or equal to 1 and less than or equal to n, and when i is greater than or equal to 2, the input data is output data of an (i−1)th layer;
determine a first complexity of the first computation instruction according to the input data, the weight data, and the first computation instruction;
determine a first data type corresponding to the first computation instruction according to the first complexity; and
determine whether to start the data type conversion circuit according to the first complexity, wherein:
the first data type is a floating point data type or a fixed point data type;
classify the input data of the first data type and the weight data of the first data type into a broadcasting data block and a distribution data block according to a type of the first computation instruction;
partition the distribution data block to obtain a plurality of basic data blocks;
distribute the plurality of basic data blocks to at least one of the plurality of basic processing circuits; and
broadcast the broadcasting data block to the plurality of basic processing circuits;
at least one of the plurality of basic processing circuits is configured to:
perform computations on the broadcasting data block of the first data type and the basic data blocks of the first data type to obtain computation results; and
transfer the computation results to the main processing circuit; and
the main processing circuit is further configured to:
process the computation results to obtain an instruction result of the first computation instruction so that computations of the first computation instruction of the ith layer are completed.
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