CPC G06F 30/394 (2020.01) [G06F 2119/12 (2020.01)] | 20 Claims |
1. A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:
constructing a clock distribution network at a first design level;
pushing at least a portion of the clock distribution network to a partition at a second design level;
constructing a partition clock tree for the partition;
calculating trial timing for the partition clock tree;
calculating combined timing of the at least a portion of the clock distribution network and the trial timing for the partition clock tree;
calculating a target constraint for the partition clock tree based on the combined timing of at least a portion of the clock distribution network and the trial timing for partition clock tree; and
calculating revised timing for the partition clock tree based on the target constraint.
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