US 11,748,548 B2
Hierarchical clock tree implementation
Hongda Lu, Austin, TX (US); Sridhar Subramaniam, San Jose, CA (US); and Kok-Hoong Chiu, Austin, TX (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 11, 2022, as Appl. No. 17/573,632.
Application 17/573,632 is a division of application No. 16/666,389, filed on Oct. 28, 2019, granted, now 11,263,379.
Claims priority of provisional application 62/863,259, filed on Jun. 18, 2019.
Prior Publication US 2022/0138395 A1, May 5, 2022
Int. Cl. G06F 30/394 (2020.01); G06F 119/12 (2020.01)
CPC G06F 30/394 (2020.01) [G06F 2119/12 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of constructing a hierarchical clock tree for an integrated circuit, the method comprising:
constructing a clock distribution network at a first design level;
pushing at least a portion of the clock distribution network to a partition at a second design level;
constructing a partition clock tree for the partition;
calculating trial timing for the partition clock tree;
calculating combined timing of the at least a portion of the clock distribution network and the trial timing for the partition clock tree;
calculating a target constraint for the partition clock tree based on the combined timing of at least a portion of the clock distribution network and the trial timing for partition clock tree; and
calculating revised timing for the partition clock tree based on the target constraint.