US 11,748,298 B2
Graphics processing integrated circuit package
Altug Koker, El Dorado Hills, CA (US); Farshad Akhbari, Chandler, AZ (US); Feng Chen, Shanghai (CN); Dukhwan Kim, Mountain View, CA (US); Narayan Srinivasa, San Jose, CA (US); Nadathur Rajagopalan Satish, Santa Clara, CA (US); Liwei Ma, Beijing (CN); Jeremy Bottleson, Carmichael, CA (US); Eriko Nurvitadhi, Hillsboro, OR (US); Joydeep Ray, Folsom, CA (US); Ping T. Tang, Edison, NJ (US); Michael S. Strickland, Sunnyvale, CA (US); Xiaoming Chen, Shanghai (CN); Tatiana Shpeisman, Menlo Park, CA (US); and Abhishek R. Appu, El Dorado Hills, CA (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 27, 2022, as Appl. No. 17/826,674.
Application 17/826,674 is a continuation of application No. 16/744,407, filed on Jan. 16, 2020, granted, now 11,360,933.
Application 16/744,407 is a continuation of application No. 15/482,796, filed on Apr. 9, 2017, granted, now 10,540,318, issued on Jan. 21, 2020.
Prior Publication US 2023/0027203 A1, Jan. 26, 2023
Int. Cl. G06F 15/80 (2006.01); G06F 13/40 (2006.01); G06T 1/20 (2006.01); G06F 9/30 (2018.01); G06F 13/00 (2006.01); G06N 3/063 (2023.01); G06N 3/084 (2023.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/048 (2023.01)
CPC G06F 15/8007 (2013.01) [G06F 9/3004 (2013.01); G06F 13/00 (2013.01); G06F 13/4027 (2013.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/048 (2023.01); G06N 3/063 (2013.01); G06N 3/084 (2013.01); G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package comprising:
a plurality of graphics processing units (GPUs) including at least a first set of one or more GPUs and a second set of one or more GPUs;
a fixed function GPU including shared function circuitry for the plurality of GPUs, the fixed function GPU being a separate processor unit from the plurality of GPUs; and
a plurality of channels, the fixed function GPU being coupled to each of the first set of one or more GPUs and the second set of one or more GPUs by a respective channel of the plurality of channels;
wherein the shared function circuitry of the fixed function GPU enables coupling between at least the first set of one or more GPUs and the second set of one or more GPUs via channels of the plurality of channels.