US 11,748,283 B1
Scalable I/O virtualization interrupt and scheduling
David Puffer, Tempe, AZ (US); Ankur Shah, Folsom, CA (US); Niranjan Cooray, Folsom, CA (US); Bryan White, Folsom, CA (US); Balaji Vembu, Folsom, CA (US); Hema Chand Nalluri, Bengaluru (IN); and Kritika Bala, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 3, 2022, as Appl. No. 17/832,305.
Claims priority of provisional application 63/321,645, filed on Mar. 18, 2022.
Int. Cl. G06F 9/48 (2006.01); G06F 12/084 (2016.01); G06F 13/24 (2006.01); G06F 13/16 (2006.01); G06T 1/20 (2006.01)
CPC G06F 13/24 (2013.01) [G06F 13/1668 (2013.01); G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A graphics processor comprising:
a system interface including a device interface configurable for assignment to a guest software domain;
a plurality of graphics engines; and
a graphics microcontroller coupled with the system interface and the plurality of graphics engines, wherein the graphics microcontroller is configured to:
receive a pointer to a memory structure in a host memory, the host memory accessible via the system interface, wherein the pointer is received for the guest software domain; and
in response to a request to schedule a workload for the guest software domain, submit the workload and the pointer to a graphics engine of the plurality of graphics engines, wherein the graphics engine is configured to access the memory structure via the pointer and configure delivery of an interrupt to the guest software domain based on data accessed via the pointer.