CPC G06F 13/1668 (2013.01) [G06F 12/023 (2013.01); G06F 2212/206 (2013.01)] | 20 Claims |
1. A system on chip (SOC), comprising:
an intellectual property (IP) core; and
a bus;
wherein the IP core is configured to:
obtain, based on an access address corresponding to an access command, an address range configuration identifier corresponding to the access address; and
transmit the access command and the address range configuration identifier to the bus; and
wherein the bus is configured to route the access command to a system cache (SC) or an external memory based on the address range configuration identifier, wherein a first path of the bus is connected to the SC, and a second path of the bus is connected to a controller for routing to the external memory.
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