US 11,748,273 B2
Secure data communication with memory sub-system
Dhawal Bavishi, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 12, 2022, as Appl. No. 17/574,117.
Application 17/574,117 is a continuation of application No. 16/694,557, filed on Nov. 25, 2019, granted, now 11,249,924.
Prior Publication US 2022/0138113 A1, May 5, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/14 (2006.01); G06F 12/02 (2006.01); H04L 9/32 (2006.01); H04L 9/06 (2006.01); H04L 9/08 (2006.01)
CPC G06F 12/1408 (2013.01) [G06F 12/0246 (2013.01); H04L 9/0643 (2013.01); H04L 9/0825 (2013.01); H04L 9/3242 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory sub-system comprising:
a set of memory devices; and
a processing device, operatively coupled to the set of memory devices, configured to perform operations comprising:
receiving, from a host system, a request to read an asymmetric public key from a particular memory address of the memory sub-system, the particular memory address being associated with a mode register of the memory sub-system;
sending, to the host system, the asymmetric public key in response to the request;
receiving, from the host system, encrypted data that comprises a first access key and a current host salt value;
decrypting, by an asymmetric private key, the encrypted data to obtain the first access key and the current host salt value from the encrypted data;
determining whether the first access key matches a second access key stored on the memory sub-system;
determining whether the current host salt value matches a current memory sub-system salt value stored on the memory sub-system; and
in response to determining that the first access key matches the second access key and the current host salt value matches the current memory sub-system salt value, granting the host system access to the set of memory devices.