US 11,748,270 B2
Tracking streaming engine vector predicates to control processor execution
Duc Quang Bui, Grand Prairie, TX (US); and Joseph Raymond Michael Zbiciak, Alviso, CA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 21, 2022, as Appl. No. 17/990,812.
Application 15/429,205 is a division of application No. 14/331,986, filed on Jul. 15, 2014, granted, now 9,606,803, issued on Mar. 28, 2017.
Application 17/990,812 is a continuation of application No. 17/187,984, filed on Mar. 1, 2021, granted, now 11,507,520.
Application 17/187,984 is a continuation of application No. 16/237,547, filed on Dec. 31, 2018, granted, now 10,936,315, issued on Mar. 2, 2021.
Application 16/237,547 is a continuation in part of application No. 16/227,238, filed on Dec. 20, 2018, granted, now 11,036,648, issued on Jun. 15, 2021.
Application 16/227,238 is a continuation of application No. 15/429,205, filed on Feb. 10, 2017, granted, now 10,162,641, issued on Dec. 25, 2018.
Claims priority of provisional application 61/846,148, filed on Jul. 15, 2013.
Prior Publication US 2023/0084716 A1, Mar. 16, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 12/1045 (2016.01); G06F 9/345 (2018.01); G06F 9/38 (2018.01); G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 7/24 (2006.01); G06F 7/487 (2006.01); G06F 7/499 (2006.01); G06F 7/53 (2006.01); G06F 7/57 (2006.01); G06F 9/48 (2006.01); G06F 17/16 (2006.01); G06F 9/32 (2018.01); G06F 12/0875 (2016.01); G06F 12/0897 (2016.01); G06F 12/0862 (2016.01); G06F 12/1009 (2016.01)
CPC G06F 12/1045 (2013.01) [G06F 7/24 (2013.01); G06F 7/487 (2013.01); G06F 7/4876 (2013.01); G06F 7/49915 (2013.01); G06F 7/53 (2013.01); G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/30014 (2013.01); G06F 9/3016 (2013.01); G06F 9/30021 (2013.01); G06F 9/30032 (2013.01); G06F 9/30036 (2013.01); G06F 9/30065 (2013.01); G06F 9/30072 (2013.01); G06F 9/30098 (2013.01); G06F 9/30112 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/32 (2013.01); G06F 9/345 (2013.01); G06F 9/3802 (2013.01); G06F 9/383 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 9/3851 (2013.01); G06F 9/3867 (2013.01); G06F 9/3887 (2013.01); G06F 9/48 (2013.01); G06F 11/00 (2013.01); G06F 11/1048 (2013.01); G06F 12/0862 (2013.01); G06F 12/0875 (2013.01); G06F 12/0897 (2013.01); G06F 12/1009 (2013.01); G06F 17/16 (2013.01); G06F 9/3822 (2013.01); G06F 11/10 (2013.01); G06F 2212/452 (2013.01); G06F 2212/60 (2013.01); G06F 2212/602 (2013.01); G06F 2212/68 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a stream instruction from a processor;
receiving a vector length parameter associated with the stream instruction;
based on the stream instruction, generating a set of addresses;
retrieving a set of data elements associated with the set of addresses from a memory;
arranging the set of data elements into a set of vectors, wherein:
a count of data elements in each vector of the set of vectors is based on the vector length parameter;
each vector of the set of vectors includes a data portion that includes at least one data element of the set of data elements and a remainder that does not include a data element of the set of data elements;
determining a respective validity indicator for each vector of the set of vectors that specifies the data portion and the remainder; and
providing a first vector of the set of vectors and a first respective validity indicator associated with the first vector to a processor.