US 11,748,267 B1
Concurrent processing of translation entry invalidation requests in a processor core
Derek E. Williams, Round Rock, TX (US); Guy L. Guthrie, Austin, TX (US); Luke Murray, Austin, TX (US); and Hugh Shen, Round Rock, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 4, 2022, as Appl. No. 17/881,469.
Int. Cl. G06F 12/0891 (2016.01); G06F 12/123 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/1027 (2013.01); G06F 12/123 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of processing in a processing unit of a data processing system, the method comprising:
buffering, in a data structure in a processor core, a plurality of entries including address translation information;
concurrently processing in the processor core a plurality of translation invalidation requests including at least first and second translation invalidation requests respectively specifying different first and second addresses, wherein the concurrently processing includes checking each of the first and second addresses against all of the plurality of entries in the data structure, and wherein the checking includes:
accessing and checking at least a first entry among the plurality of entries in the data structure for an address match with the first address but not the second address;
thereafter, accessing at least a second entry among the plurality of entries in the data structure and concurrently checking said at least second entry for an address match with both the first and second addresses;
thereafter, completing checking against the plurality of entries for the first address and accessing and checking the first entry for an address match with the second address but not the first address; and
invalidating any entry in the data structure for which the checking detects an address match.