CPC G06F 11/3688 (2013.01) [G01R 31/3177 (2013.01); G01R 31/31813 (2013.01); G06F 3/0484 (2013.01); G06F 9/4881 (2013.01); G06F 11/2205 (2013.01); G06F 11/25 (2013.01); G06F 11/263 (2013.01); G06F 30/20 (2020.01); G06F 30/331 (2020.01); G06F 30/3323 (2020.01); G06F 30/39 (2020.01); G06T 11/206 (2013.01)] | 19 Claims |
1. A method for testing a system-on-a-chip (SoC), comprising:
receiving a plurality of application scenario models, wherein the plurality of application scenario models are associated with a plurality of expected results, wherein each of the plurality of expected results is back propagated via a corresponding one of the plurality of application scenario models to generate a stimulus at an input of the corresponding one of the plurality of application scenario models,
wherein the plurality of application scenario models include a first application scenario model and a second application scenario model, wherein the first application scenario model includes a first plurality of driver scenario models coupled in series and the second application scenario model includes a second plurality of driver scenario models coupled in series, wherein the first plurality of driver scenario models and the second plurality of driver scenario models have at least one driver scenario model in common;
dividing the plurality of application scenario models between a plurality of processing units; and
controlling the plurality of processing units to apply the stimuli to the plurality of application scenario models to facilitate generation of a plurality of test results, wherein the plurality of test results are used for said testing of the SoC.
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