US 11,748,194 B2
Error correcting memory systems
Yu Lu, San Diego, CA (US); and Chieh-yu Lin, San Diego, CA (US)
Assigned to SuperMem, Inc., San Diego, CA (US)
Filed by SuperMem, Inc., San Diego, CA (US)
Filed on Dec. 17, 2021, as Appl. No. 17/554,505.
Application 17/554,505 is a continuation of application No. 17/284,642, granted, now 11,204,835, issued on Dec. 21, 2021, previously published as PCT/US2019/055963, filed on Oct. 11, 2019.
Claims priority of provisional application 62/886,967, filed on Aug. 15, 2019.
Claims priority of provisional application 62/755,702, filed on Nov. 5, 2018.
Claims priority of provisional application 62/745,204, filed on Oct. 12, 2018.
Prior Publication US 2022/0188187 A1, Jun. 16, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); G11C 29/52 (2006.01); G11C 11/16 (2006.01)
CPC G06F 11/1068 (2013.01) [G11C 29/52 (2013.01); G11C 11/161 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a data memory;
an ECC memory; and
a data scrubbing circuit electrically coupled to the ECC memory and the data memory,
wherein the data scrubbing circuit is configured to:
receive a protect command for data; and
in response to receiving the protect command, for each data word in the data to be protected:
perform ECC encoding computation on the data word;
generate ECC check bits based on the ECC encoding computation; and
write the generated ECC check bits to a corresponding partition in the ECC memory.