US 11,748,190 B2
Cyclic redundancy check computation circuit, communication unit, and method therefor
Robert Maunder, Southampton (GB); and Matthew Brejza, Southampton (GB)
Assigned to Accelercomm Ltd, Southampton (GB)
Appl. No. 17/623,428
Filed by ACCELERCOMM LTD, Southampton (GB)
PCT Filed Jun. 30, 2020, PCT No. PCT/EP2020/068425
§ 371(c)(1), (2) Date Dec. 28, 2021,
PCT Pub. No. WO2021/001381, PCT Pub. Date Jan. 7, 2021.
Claims priority of application No. 1909489 (GB), filed on Jul. 1, 2019.
Prior Publication US 2022/0350697 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/10 (2006.01); H03M 13/09 (2006.01)
CPC G06F 11/1004 (2013.01) [H03M 13/091 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A cyclic redundancy check, CRC, computation circuit comprising:
an input for receiving an input stream that has an input bit sequence comprising two or more bits of the input stream at a time that are aligned to the rows of a CRC generator matrix stored in a Look Up Table, LUT;
a set of two or more parallel processors configured to perform a CRC computation of the input bit sequence;
wherein the LUT, is operably coupled to the set of two or more parallel processors and comprises a plurality of addresses wherein at least one of the plurality of addresses is configured to store two or more rows of the CRC generator matrix; and
the set of two or more parallel processors is configured to:
combine LUT data with the input stream by using two or more bits of the aligned input stream to mask the two or more rows of the CRC generator matrix stored in the LUT and thereby generate two or more intermediate parity bit sequences; and
combine the two or more intermediate parity bit sequences into a single parity bit sequence.