US 11,748,112 B2
Configurable media structure
Reshmi Basu, Boise, ID (US); and Richard C. Murphy, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 14, 2022, as Appl. No. 17/576,546.
Application 17/576,546 is a continuation of application No. 16/546,416, filed on Aug. 21, 2019, granted, now 11,237,841.
Prior Publication US 2022/0137980 A1, May 5, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/4401 (2018.01); G06F 11/14 (2006.01); G11C 11/56 (2006.01); G06F 12/02 (2006.01); G06F 11/10 (2006.01); G11C 7/20 (2006.01); G11C 16/20 (2006.01)
CPC G06F 9/441 (2013.01) [G06F 11/102 (2013.01); G06F 11/1417 (2013.01); G06F 12/0238 (2013.01); G11C 11/5628 (2013.01); G06F 2212/7201 (2013.01); G11C 7/20 (2013.01); G11C 16/20 (2013.01)] 20 Claims
OG exemplary drawing
 
8. An apparatus comprising:
a first memory array;
a second memory array; and
a controller coupled to the first memory array and the second memory array;
wherein:
the second memory array is configured to store a first boot image and a second boot image;
the first boot image is used to operate the first memory array in a non-volatile memory configuration;
the second boot image is used to operate the first memory array in a volatile memory configuration; and
an error correction rate is increased and a latency rate is decreased based on whether the memory device is booted up using the first boot image or the second boot image.