CPC G06F 9/441 (2013.01) [G06F 11/102 (2013.01); G06F 11/1417 (2013.01); G06F 12/0238 (2013.01); G11C 11/5628 (2013.01); G06F 2212/7201 (2013.01); G11C 7/20 (2013.01); G11C 16/20 (2013.01)] | 20 Claims |
8. An apparatus comprising:
a first memory array;
a second memory array; and
a controller coupled to the first memory array and the second memory array;
wherein:
the second memory array is configured to store a first boot image and a second boot image;
the first boot image is used to operate the first memory array in a non-volatile memory configuration;
the second boot image is used to operate the first memory array in a volatile memory configuration; and
an error correction rate is increased and a latency rate is decreased based on whether the memory device is booted up using the first boot image or the second boot image.
|