US 11,748,108 B2
Instruction executing method and apparatus, electronic device, and computer-readable storage medium
Yingnan Xu, Beijing (CN); Jian Ouyang, Beijing (CN); Xueliang Du, Beijing (CN); and Kang An, Beijing (CN)
Assigned to Beijing Baidu Netcom Science and Technology Co., LTD., Beijing (CN); and Kunlunxin Technology (Beijing) Company Limited, Beijing (CN)
Filed by Beijing Baidu Netcom Science and Technology Co., Ltd., Beijing (CN); and Kunlunxin Technology (Beijing) Company Limited, Beijing (CN)
Filed on Mar. 24, 2021, as Appl. No. 17/210,616.
Claims priority of application No. 202010699439.3 (CN), filed on Jul. 20, 2020.
Prior Publication US 2021/0271482 A1, Sep. 2, 2021
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3834 (2013.01) [G06F 9/30087 (2013.01); G06F 9/3838 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An instruction executing method, comprising:
executing an instruction sequence, the instruction sequence comprising memory instructions and non-memory instructions, wherein the instructions in the instruction sequence are initially executed in order;
determining that execution of a first memory instruction needs to be completed before a second memory instruction starts to be executed, the second memory instruction being a next memory instruction following the first memory instruction in the instruction sequence; and
executing non-memory instructions between the first memory instruction and the second memory instruction, before executing the second memory instruction and during execution of the first memory instruction;
wherein, the instruction sequence further comprises a halt instruction, and
in a case where the halt instruction is executed, determining a memory instruction corresponding to the halt instruction is the first memory instruction;
wherein, the halt instruction immediately follows the first memory instruction, and in a case where the halt instruction is executed, the execution of the first memory instruction needs to be completed before the second memory instruction starts to be executed;
wherein, in a case where the halt instruction is executed, non-memory instructions between the halt instruction and the second memory instruction are executed.