US 11,748,107 B2
Complex I/O value prediction for multiple values with physical or virtual addresses
Jason D. Zebchuk, Edinburgh (GB); Wilson P. Snyder, II, Holliston, MA (US); and Michael S. Bertone, Marlborough, MA (US)
Assigned to Marvell Asia Pte, Ltd., Singapore (SG)
Filed by Marvell Asia Pte, Ltd., Singapore (SG)
Filed on Nov. 22, 2022, as Appl. No. 18/58,023.
Application 18/058,023 is a continuation of application No. 16/209,739, filed on Dec. 4, 2018, granted, now 11,573,800.
Claims priority of provisional application 62/694,414, filed on Jul. 5, 2018.
Prior Publication US 2023/0080128 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 12/10 (2016.01); G06F 9/48 (2006.01)
CPC G06F 9/3832 (2013.01) [G06F 9/30043 (2013.01); G06F 9/4881 (2013.01); G06F 9/5077 (2013.01); G06F 12/10 (2013.01); G06F 9/3004 (2013.01); G06F 2212/65 (2013.01)] 23 Claims
OG exemplary drawing
 
13. A method comprising:
generating, by a processor core, an I/O instruction for an I/O device, the I/O device including a state machine with state transition logic;
transmitting the I/O instruction generated to the I/O device;
predicting at least one state value of at least one I/O device true state value to be affected by the I/O instruction at the I/O device, the predicting including employing a simplified state machine with a reduced version of the state transition logic of the state machine of the I/O device; and
employing, by the processor core, the at least one state value predicted.