CPC G06F 9/30178 (2013.01) [G06F 9/3013 (2013.01); G06F 9/30036 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01)] | 20 Claims |
1. A processor comprising:
fetch circuitry to fetch a single compress instruction having a format with fields to specify an opcode, a location of a decompressed source matrix, and a location of a compressed destination matrix;
decode circuitry to decode the fetched single compress instruction; and
execution circuitry, responsive to the decoded single compress instruction, to:
generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by packing non-zero-valued elements together;
store a matrix position of each non-zero-valued element in a header; and
store the compressed result to the specified compressed destination matrix.
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