US 11,748,103 B2
Systems and methods for performing matrix compress and decompress instructions
Dan Baum, Haifa (IL); Michael Espig, Newberg, OR (US); James Guilford, Northborough, MA (US); Wajdi K. Feghali, Boston, MA (US); Raanan Sade, Kibutz Sarid (IL); Christopher J. Hughes, Santa Clara, CA (US); Robert Valentine, Kiryat Tivon (IL); Bret Toll, Hillsboro, OR (US); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Mark J. Charney, Lexington, MA (US); Vinodh Gopal, Westborough, MA (US); Ronen Zohar, Sunnyvale, CA (US); and Alexander F. Heinecke, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 15, 2022, as Appl. No. 17/672,253.
Application 17/672,253 is a continuation of application No. 16/934,003, filed on Jul. 20, 2020, granted, now 11,249,761, issued on Feb. 5, 2022.
Application 16/934,003 is a continuation of application No. 16/144,902, filed on Sep. 27, 2018, granted, now 10,719,323, issued on Jul. 21, 2020.
Prior Publication US 2022/0171627 A1, Jun. 2, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30178 (2013.01) [G06F 9/3013 (2013.01); G06F 9/30036 (2013.01); G06F 9/30145 (2013.01); G06F 9/3802 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
fetch circuitry to fetch a single compress instruction having a format with fields to specify an opcode, a location of a decompressed source matrix, and a location of a compressed destination matrix;
decode circuitry to decode the fetched single compress instruction; and
execution circuitry, responsive to the decoded single compress instruction, to:
generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by packing non-zero-valued elements together;
store a matrix position of each non-zero-valued element in a header; and
store the compressed result to the specified compressed destination matrix.