CPC G06F 8/52 (2013.01) [G06F 9/30101 (2013.01)] | 12 Claims |
1. A method comprising:
decoding, by a computer system, a first source code fragment compatible with a source instruction set architecture (ISA);
translating, using a register mapping table, the first source code fragment into a first target code fragment compatible with a target ISA, wherein the register mapping table comprises a plurality of register mapping entries, each register mapping entry specifying a source register and a target register representing the source register in the first target code fragment;
decoding a second source code fragment compatible with the source ISA; and
modifying, based on decoding the second source code fragment, at least one register mapping entry of the register mapping table; wherein
each register mapping entry of the register mapping table further comprises a weight value indicative of a number of binary translation iterations that were performed after a corresponding target register was utilized.
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