CPC G06F 3/0659 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
1. A memory controller, comprising:
a heterogenous memory channel interface for coupling to a non-volatile memory and a volatile memory over a heterogenous memory channel;
a non-volatile command queue (NV queue) for storing non-volatile read commands that are sent over the heterogenous memory channel;
an arbiter for selecting from among memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes, and causing them to be transmitted over the heterogenous memory channel; and
a control circuit adapted to be coupled to the heterogenous memory channel interface for receiving a ready response from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands, and in response to receiving the ready response, causing a send command to be transmitted for commanding the non-volatile memory to send the responsive data.
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