US 11,748,034 B2
Signalling for heterogeneous memory systems
James R. Magro, Austin, TX (US); and Kedarnath Balakrishnan, Bangalore (IN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Aug. 23, 2021, as Appl. No. 17/409,099.
Application 17/409,099 is a continuation of application No. 16/730,070, filed on Dec. 30, 2019, granted, now 11,099,786.
Prior Publication US 2021/0382661 A1, Dec. 9, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a heterogenous memory channel interface for coupling to a non-volatile memory and a volatile memory over a heterogenous memory channel;
a non-volatile command queue (NV queue) for storing non-volatile read commands that are sent over the heterogenous memory channel;
an arbiter for selecting from among memory access commands including volatile memory reads, volatile memory writes, non-volatile memory reads, and non-volatile memory writes, and causing them to be transmitted over the heterogenous memory channel; and
a control circuit adapted to be coupled to the heterogenous memory channel interface for receiving a ready response from the non-volatile memory indicating that responsive data is available for an associated one of the non-volatile read commands, and in response to receiving the ready response, causing a send command to be transmitted for commanding the non-volatile memory to send the responsive data.