US 11,748,033 B2
Transaction management using metadata
Chinnakrishnan Ballapuram, San Jose, CA (US); Kang-Yong Kim, Boise, ID (US); Saira Samar Malik, Lafayette, IN (US); and Taeksang Song, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 30, 2021, as Appl. No. 17/390,093.
Claims priority of provisional application 63/060,382, filed on Aug. 3, 2020.
Prior Publication US 2022/0035568 A1, Feb. 3, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 12/0238 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a volatile memory;
a non-volatile memory; and
an interface controller coupled with the volatile memory and the non-volatile memory, wherein the interface controller is operable to:
receive, from a host device, a read command for a first set of data, the read command associated with a latency for returning the first set of data to the host device;
determine, in response to receiving the read command, that the first set of data is stored in the non-volatile memory and not the volatile memory; and
transmit concurrently, to the host device, a first subset of a second set of data according to the latency for returning the first set of data and a signal that indicates whether the second set of data was requested by the host device.