US 11,748,021 B2
Scrub rate control for a memory device
Aaron P. Boehm, Boise, ID (US); and Debra M. Bell, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 3, 2021, as Appl. No. 17/518,164.
Application 17/518,164 is a continuation of application No. 16/433,891, filed on Jun. 6, 2019, granted, now 11,169,730.
Prior Publication US 2022/0129185 A1, Apr. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01)
CPC G06F 3/0652 (2013.01) [G06F 3/0616 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 11/1076 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, from a host device, a first plurality of scrub commands according to a first rate for scrubbing a memory array of a memory device;
performing, at the memory device, a plurality of scrub operations based at least in part on receiving the first plurality of scrub commands;
monitoring, during the plurality of scrub operations, one or more bit errors detected for a plurality of rows of the memory array of the memory device for each scrub operation;
determining first quantities of bit errors detected during the plurality of scrub operations based at least in part on the monitoring;
transmitting, to the host device, an indicator of a condition of the memory array, the condition of the memory array associated with a level of integrity of data stored at the memory array and based at least in part on comparing a first metric associated with the first quantities of the bit errors to a second metric, wherein the first metric corresponds to a first average of the first quantities of bit errors, a change in the first quantities of bit errors, a rate of change of the first quantities of bit errors, or any combination thereof, and wherein the second metric corresponds to a second average of second quantities of bit errors, a second change in the second quantities of bit errors, a second rate of change of the second quantities of bit errors, or any combination thereof; and
receiving, from the host device after transmitting the indicator of the condition of the memory array to the host device, a second plurality of scrub commands according to a second rate for scrubbing the memory array that is greater than the first rate, wherein the first rate for scrubbing the memory array is based at least in part on one or more first quantities of rows associated with the first plurality of scrub commands, and wherein the second rate for scrubbing the memory array is based at least in part on one or more second quantities of rows associated with the second plurality of scrub commands.