US 11,748,013 B2
Grouping blocks based on power cycle and power on time
Kishore Kumar Muchherla, San Jose, CA (US); Mustafa N. Kaynak, San Diego, CA (US); Jiangang Wu, Milpitas, CA (US); Sampath K. Ratnam, San Jose, CA (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Peter Feeley, Boise, ID (US); and Karl D. Schuh, Santa Cruz, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 21, 2022, as Appl. No. 17/949,977.
Application 17/949,977 is a continuation of application No. 17/153,233, filed on Jan. 20, 2021, granted, now 11,500,564.
Prior Publication US 2023/0017591 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 16/10 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processor, operatively coupled to the memory device, the processor to perform operations comprising:
identifying an initial value of a power cycle count associated with the memory device, wherein the power cycle count is incremented responsive to detecting a powering up of the memory device;
responsive to programming a block residing on the memory device, associating the block with a current block family associated with the memory device;
determining a current value of the power cycle count; and
responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, closing the current block family.