CPC G06F 3/0635 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G11C 29/76 (2013.01)] | 11 Claims |
1. A memory system, comprising:
a memory; and
a memory controller suitable for controlling the memory,
wherein the memory comprises:
a non-volatile memory suitable for storing a defect address;
a register suitable for receiving and storing the defect address from the non-volatile memory during a boot-up operation, and receiving and storing an address that is input from the memory controller during a register access operation;
a comparison circuit suitable for comparing the address stored in the register with an address that is input from the memory controller to produce a comparison result;
redundant memory cells that are accessed according to the comparison result of the comparison circuit and a redundancy activation bit; and
normal memory cells that are accessed according to the comparison result of the comparison circuit and the redundancy activation bit, and
wherein the memory controller is further suitable for:
detecting a defect in the normal memory cells of the memory,
storing an address corresponding to the defect in the register,
reading data of defective memory cells among the normal memory cells by deactivating the redundancy activation bit and storing the read data in a cache, and
writing the data of the cache into the redundant memory cells by activating the redundancy activation bit.
|