US 11,748,007 B2
Memory, memory system, and operation method of memory system
Munseon Jang, San Jose, CA (US); Hoiju Chung, San Jose, CA (US); and Jang Ryul Kim, San Jose, CA (US)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jun. 22, 2021, as Appl. No. 17/354,482.
Claims priority of provisional application 63/178,320, filed on Apr. 22, 2021.
Claims priority of provisional application 63/042,208, filed on Jun. 22, 2020.
Prior Publication US 2021/0397355 A1, Dec. 23, 2021
Int. Cl. G06F 3/06 (2006.01); G11C 29/00 (2006.01)
CPC G06F 3/0635 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0655 (2013.01); G06F 3/0673 (2013.01); G11C 29/76 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory; and
a memory controller suitable for controlling the memory,
wherein the memory comprises:
a non-volatile memory suitable for storing a defect address;
a register suitable for receiving and storing the defect address from the non-volatile memory during a boot-up operation, and receiving and storing an address that is input from the memory controller during a register access operation;
a comparison circuit suitable for comparing the address stored in the register with an address that is input from the memory controller to produce a comparison result;
redundant memory cells that are accessed according to the comparison result of the comparison circuit and a redundancy activation bit; and
normal memory cells that are accessed according to the comparison result of the comparison circuit and the redundancy activation bit, and
wherein the memory controller is further suitable for:
detecting a defect in the normal memory cells of the memory,
storing an address corresponding to the defect in the register,
reading data of defective memory cells among the normal memory cells by deactivating the redundancy activation bit and storing the read data in a cache, and
writing the data of the cache into the redundant memory cells by activating the redundancy activation bit.