US 11,747,992 B2
Memory wear management
Saira Samar Malik, Lafayette, IN (US); Hyunyoo Lee, Boise, ID (US); Chinnakrishnan Ballapuram, San Jose, CA (US); Taeksang Song, San Jose, CA (US); and Kang-Yong Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 16, 2021, as Appl. No. 17/349,634.
Claims priority of provisional application 63/050,283, filed on Jul. 10, 2020.
Prior Publication US 2022/0011944 A1, Jan. 13, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7211 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a non-volatile memory comprising a memory bank; and
an interface controller coupled with the non-volatile memory and operable to cause the apparatus to:
select a physical row address in the memory bank for a procedure that moves data from a first row of the memory bank to a second row of the memory bank;
determine to initiate the procedure for the first row of the memory bank based at least in part on the physical row address, wherein the physical row address is associated with the first row;
issue, to the non-volatile memory as part of the procedure, a read command for the physical row address associated with the first row;
store the data in the second row of the memory bank based at least in part on issuing the read command; and
update one or more pointers in a register of the interface controller based at least in part on storing the data in the second row of the memory bank.