CPC G06F 3/0613 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] | 20 Claims |
1. A semiconductor memory apparatus comprising:
a memory bank circuit configured to store normal data, an error correction code, and a meta information code; and
a bandwidth control circuit configured to set a ratio between a memory region of the memory bank circuit in which the error correction code is to be stored and a memory region of the memory bank circuit in which the meta information code is to be stored by controlling transmission bandwidths of the error correction code and the meta information code based on bandwidth option information.
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