US 11,747,988 B2
Semiconductor memory apparatus and semiconductor memory system for controlling transmission bandwidth
Chang Yong Ahn, Icheon-si (KR); and Sung Hak Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 29, 2021, as Appl. No. 17/537,172.
Claims priority of application No. 10-2021-0098687 (KR), filed on Jul. 27, 2021.
Prior Publication US 2023/0032148 A1, Feb. 2, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory apparatus comprising:
a memory bank circuit configured to store normal data, an error correction code, and a meta information code; and
a bandwidth control circuit configured to set a ratio between a memory region of the memory bank circuit in which the error correction code is to be stored and a memory region of the memory bank circuit in which the meta information code is to be stored by controlling transmission bandwidths of the error correction code and the meta information code based on bandwidth option information.