US 11,747,985 B2
Memory system, integrated circuit system, and operation method of memory system
Munseon Jang, San Jose, CA (US); and Hoiju Chung, San Jose, CA (US)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 21, 2021, as Appl. No. 17/507,442.
Application 17/507,442 is a continuation in part of application No. 16/939,741, filed on Jul. 27, 2020, granted, now 11,322,219.
Claims priority of provisional application 62/944,586, filed on Dec. 6, 2019.
Prior Publication US 2022/0043580 A1, Feb. 10, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 11/10 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 11/1048 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory, comprising:
a memory core;
an error correction circuit suitable for correcting, when a number of one or more errors detected in data read from the memory core is equal to or greater than a threshold value, the detected errors based on an error correction code read from the memory core to produce an error-corrected data; and
a data transferring circuit suitable for:
outputting, when the detected errors are corrected, the error-corrected data according to a long read latency, and
outputting, when the number of the detected errors is less than the threshold value or no error is detected in the read data, the read data according to a short read latency.