US 11,747,856 B2
Asynchronous ASIC
Niv Margalit, Ramat-Hasharon (IL); and Eyal Sela, Ramat-Hasharon (IL)
Assigned to Magic Leap, Inc., Plantation, FL (US)
Filed by Magic Leap, Inc., Plantation, FL (US)
Filed on Feb. 27, 2023, as Appl. No. 18/175,466.
Application 18/175,466 is a continuation of application No. 17/950,808, filed on Sep. 22, 2022, granted, now 11,619,965.
Application 17/950,808 is a continuation of application No. 17/288,457, granted, now 11,487,316, issued on Nov. 1, 2022, previously published as PCT/US2019/057723, filed on Oct. 23, 2019.
Claims priority of provisional application 62/750,180, filed on Oct. 24, 2018.
Prior Publication US 2023/0205257 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/06 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); H03L 7/081 (2006.01)
CPC G06F 1/12 (2013.01) [G06F 1/06 (2013.01); G06F 1/10 (2013.01); H03L 7/0816 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device comprising:
first circuitry configured to synchronize with a first clock, the first clock configured to operate at a frequency; and
second circuitry configured to generate a second clock and a third clock based on the first clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
the second clock and third clock are selected from a plurality of clock candidates;
wherein:
each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
selecting the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
selecting the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.