CPC G06F 1/12 (2013.01) [G06F 1/06 (2013.01); G06F 1/10 (2013.01); H03L 7/0816 (2013.01)] | 20 Claims |
1. An electronic device comprising:
first circuitry configured to synchronize with a first clock, the first clock configured to operate at a frequency; and
second circuitry configured to generate a second clock and a third clock based on the first clock, wherein:
the second clock is configured to operate at the frequency of the first clock and further configured to operate with a first phase shift with respect to the first clock,
the third clock is configured to operate at the frequency of the first clock and further configured to operate with a second phase shift with respect to the first clock, and
the second clock and third clock are selected from a plurality of clock candidates;
wherein:
each clock candidate of the plurality of clock candidates is associated with a respective phase shift relative to the first clock;
selecting the second clock from the plurality of clock candidates comprises comparing, for a first data bit of a plurality of data bits, a first respective phase shift to a transition edge of the first clock; and
selecting the third clock from the plurality of clock candidates comprises comparing, for a second data bit of the plurality of data bits, a second respective phase shift to a transition edge of the first clock.
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