US 11,747,853 B2
Semiconductor device, semiconductor system and method for operating semiconductor device
Ho Yeon Jeon, Hwaseong-si (KR); Ah Chan Kim, Hwaseong-si (KR); and Jae Gon Lee, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (unknown)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 5, 2022, as Appl. No. 17/713,656.
Application 17/713,656 is a continuation of application No. 17/154,373, filed on Jan. 21, 2021, granted, now 11,314,278.
Application 17/154,373 is a continuation of application No. 16/393,106, filed on Apr. 24, 2019, granted, now 10,928,849, issued on Feb. 23, 2021.
Application 16/393,106 is a continuation of application No. 15/414,819, filed on Jan. 25, 2017, granted, now 10,303,203, issued on May 28, 2019.
Claims priority of provisional application 62/286,860, filed on Jan. 25, 2016.
Claims priority of provisional application 62/286,882, filed on Jan. 25, 2016.
Claims priority of application No. 10-2017-0000609 (KR), filed on Jan. 3, 2017; and application No. 10-2017-0010945 (KR), filed on Jan. 24, 2017.
Prior Publication US 2022/0229464 A1, Jul. 21, 2022
Int. Cl. G06F 1/10 (2006.01); G06F 1/32 (2019.01); G06F 1/3237 (2019.01)
CPC G06F 1/10 (2013.01) [G06F 1/3237 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system on chip (SoC) comprising:
a first intellectual property (IP) block;
a second IP block;
a first channel management circuit configured to transmit a first request signal to the first IP block and receive a first response signal from the first IP block; and
a second channel management circuit configured to transmit a second request signal to the second IP block and receive a second response signal from the second IP block and receive the first response signal from the first IP block,
wherein the first channel management circuit is configured to transmit a first clock request signal to the second channel management circuit in response to the first response signal, and the second channel management circuit is configured to transmit a first clock acknowledgment signal to the first channel management circuit in response to the first clock request signal.