CPC G06F 1/10 (2013.01) [G06F 1/3237 (2013.01)] | 20 Claims |
1. A system on chip (SoC) comprising:
a first intellectual property (IP) block;
a second IP block;
a first channel management circuit configured to transmit a first request signal to the first IP block and receive a first response signal from the first IP block; and
a second channel management circuit configured to transmit a second request signal to the second IP block and receive a second response signal from the second IP block and receive the first response signal from the first IP block,
wherein the first channel management circuit is configured to transmit a first clock request signal to the second channel management circuit in response to the first response signal, and the second channel management circuit is configured to transmit a first clock acknowledgment signal to the first channel management circuit in response to the first clock request signal.
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