US 11,747,786 B2
Synchronized parallel tile computation for large area lithography simulation
Danping Peng, Fremont, CA (US); Junjiang Lei, Fremont, CA (US); Daniel Beylkin, San Jose, CA (US); Kenneth Lik Kin Ho, Redwood City, CA (US); Sagar Trivedi, Santa Clara, CA (US); and Fangbo Xu, San Jose, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on May 23, 2022, as Appl. No. 17/750,828.
Application 17/750,828 is a division of application No. 17/170,389, filed on Feb. 8, 2021, granted, now 11,340,584.
Application 17/170,389 is a division of application No. 16/889,514, filed on Jun. 1, 2020, granted, now 10,915,090, issued on Feb. 9, 2021.
Application 16/889,514 is a division of application No. 15/867,437, filed on Jan. 10, 2018, granted, now 10,671,052, issued on Jun. 2, 2020.
Claims priority of provisional application 62/586,621, filed on Nov. 15, 2017.
Prior Publication US 2022/0291659 A1, Sep. 15, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/392 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G03F 1/70 (2012.01); G03F 1/36 (2012.01); G03F 1/24 (2012.01); G05B 19/4097 (2006.01); G21K 5/00 (2006.01); G06F 111/20 (2020.01); G06F 119/18 (2020.01)
CPC G05B 19/4097 (2013.01) [G03F 1/24 (2013.01); G03F 1/36 (2013.01); G03F 1/70 (2013.01); G06F 30/392 (2020.01); G05B 2219/35012 (2013.01); G05B 2219/45027 (2013.01); G05B 2219/45028 (2013.01); G05B 2219/45031 (2013.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 2111/20 (2020.01); G06F 2119/18 (2020.01); G21K 5/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a manager machine interacting with a plurality of worker machines,
wherein the manager machine is configured to:
receive an IC design layout;
partition the IC design layout into a plurality of tiles;
assign the plurality of tiles to the plurality of worker machines; and
wherein the plurality of worker machines interact with the manager machine and are configured to synchronize image values from the plurality of tiles;
wherein the manager machine is further configured to:
generate a modified IC design layout by combining final synchronized image values from the plurality of worker machines; and
provide the modified IC design layout for fabricating a mask.