US 11,114,170 B2
Memory system
Takaya Handa, Yokohama Kanagawa (JP); Yoshihisa Kojima, Kawasaki Kanagawa (JP); and Kiyotaka Iwasaki, Yokohama Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on May 28, 2020, as Appl. No. 16/886,546.
Application 16/886,546 is a continuation of application No. 16/115,516, filed on Aug. 28, 2018, granted, now 10,706,940.
Claims priority of application No. JP2017-251367 (JP), filed on Dec. 27, 2017.
Prior Publication US 2020/0294605 A1, Sep. 17, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/32 (2006.01); G11C 16/24 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 7/106 (2013.01); G11C 7/1063 (2013.01); G11C 7/1069 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01); G11C 7/222 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells, each memory cell being capable of storing data;
a sense circuit configured to sense the data stored in a memory cell of the plurality of memory cells;
a first data latch configured to latch data sensed from the memory cell by the sense circuit;
a second data latch configured to receive the data from the first data latch;
a status register configured to store information indicating whether the semiconductor memory device is in a ready state or in a busy state;
an input/output circuit configured to output from the semiconductor memory device the data received from the second data latch and the information received from the status register; and
a control circuit configured to control the status register to store the information indicating the busy state upon receipt of a read command and to control the status register to store the information indicating the ready state, before completion of transfer of the data sensed from the memory cell from the first data latch to the second data latch.