CPC H10N 60/128 (2023.02) [G06N 10/20 (2022.01); G06N 10/40 (2022.01); H03K 17/92 (2013.01); H10N 60/01 (2023.02); H10N 60/11 (2023.02); H10N 69/00 (2023.02)] | 16 Claims |
1. A device including at least:
a semiconductor layer comprising first regions, second regions arranged such that each of the first regions is delimited by two of the second regions aligned parallel to a first direction and that two of the neighbouring first regions aligned parallel to the first direction are delimited by one of the second regions, and third regions arranged such that each of the first regions is delimited by two of the third regions aligned parallel to a second direction different from the first direction and that two of the first regions aligned parallel to the second direction are delimited by one of the third regions;
first electrostatic control gates including first conductive portions extending parallel to the second direction, in vertical alignment with the second regions;
second electrostatic control gates including second conductive portions extending parallel to the first direction, in vertical alignment with the third regions;
wherein each first gate includes an electrostatic control voltage adjustment element forming first and second impedances connected in series to each other through their first ends, a second end of the first impedance being electrically coupled to the first conductive portion of the first gate and a second end of the second impedance being electrically coupled to a third conductive portion, and wherein the value of at least one of the first and second impedances is adjustable.
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