US 11,737,368 B2
Magnetic memory devices and methods of fabrication
Daniel Ouellette, Portland, OR (US); Christopher Wiegand, Portland, OR (US); Justin Brockman, Portland, OR (US); Tofizur Rahman, Portland, OR (US); Oleg Golonzka, Beaverton, OR (US); Angeline Smith, Hillsboro, OR (US); Andrew Smith, Hillsboro, OR (US); James Pellegren, Portland, OR (US); Michael Robinson, Beaverton, OR (US); and Huiying Liu, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 27, 2019, as Appl. No. 16/367,136.
Prior Publication US 2020/0313084 A1, Oct. 1, 2020
Int. Cl. H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC H10N 50/01 (2023.02) [H10B 61/22 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first electrode;
a conductive layer comprising iridium and one of iron or cobalt, the conductive layer above the first electrode, wherein a concentration of the iron or the cobalt varies from an uppermost surface to a lowermost surface of the conductive layer;
a magnetic junction on the conductive layer, the magnetic junction comprising:
a magnetic structure comprising a stack of bilayers, wherein each bilayer comprises a magnetic layer and a non-magnetic layer on the magnetic layer;
a spacer layer on the magnetic structure;
a first magnet with a first magnetization on the spacer layer;
a second magnet with a second magnetization, the second magnet above the first magnet; and
a layer between the first magnet and the second magnet; and
a second electrode above the magnetic junction.