US 11,737,271 B2
Semiconductor memory device with a plurality of amplification stages
Tae-Hong Kwon, Seoul (KR); Chan Ho Kim, Seoul (KR); Kyung Hwa Yun, Hwaseong-si (KR); Dae Seok Byeon, Seongnam-si (KR); and Chi Weon Yoon, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 14, 2020, as Appl. No. 16/993,570.
Claims priority of application No. 10-2019-0169839 (KR), filed on Dec. 18, 2019.
Prior Publication US 2021/0193679 A1, Jun. 24, 2021
Int. Cl. H10B 43/27 (2023.01); G11C 16/32 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 5/14 (2006.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 5/145 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a cell array structure;
a peripheral logic structure comprising a first region comprising a first region of a substrate and a second region comprising a second region of the substrate, wherein the first region of the peripheral logic structure is disposed directly below the cell array structure;
first lower wirings disposed in the first region of the substrate;
second lower wirings disposed in the second region of the substrate;
a stacked structure, wherein the stacked structure is disposed on the first lower wirings, and the stacked structure comprises an interlayer insulating film and an electrode pad alternately stacked in a direction perpendicular to the substrate;
a vertical structure penetrating the stacked structure;
a tunnel insulating layer extending along sidewalls of the vertical structure;
a charge storage layer extending along sidewalls of the tunnel insulating layer;
a plurality of through vias disposed on the second lower wirings and disposed in the second region of peripheral logic structure, wherein the plurality of through vias are configured to electrically connect the second lower wirings and upper wirings, wherein the upper wirings are disposed in the second region of the peripheral logic structure;
a first amplification stage comprising the first lower wirings and configured to generate a first operating voltage to be applied to the electrode pad; and
a second amplification stage comprising the second lower wirings and the plurality of through vias, electrically connected to the first amplification stage, and configured to generate a second operating voltage to be applied to the electrode pad,
wherein the second region of the peripheral logic structure comprises a metal-insulator-metal (MIM) capacitor disposed above the plurality of through vias.