US 11,737,253 B2
Uniform layouts for SRAM and register file bit cells
Zheng Guo, Portland, OR (US); Clifford L. Ong, Portland, OR (US); Eric A. Karl, Portland, OR (US); and Mark T. Bohr, Aloha, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/605,903
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Jun. 22, 2017, PCT No. PCT/US2017/038681
§ 371(c)(1), (2) Date Oct. 17, 2019,
PCT Pub. No. WO2018/236377, PCT Pub. Date Dec. 27, 2018.
Prior Publication US 2020/0058656 A1, Feb. 20, 2020
Int. Cl. H10B 10/00 (2023.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01)
CPC H10B 10/12 (2023.02) [H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a substrate;
a six transistor (6T) static random access memory (SRAM) bit cell on the substrate, the 6T SRAM bit cell comprising:
first and second active regions parallel along a first direction of the substrate; and
first, second, third and fourth gate lines over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction, wherein all of the first, second, third and fourth gate lines vertically overlap one of the first active region or the second active region, and wherein at least two of the first, second, third or fourth gate lines vertically overlap both of the first active region and the second active region.