US 11,737,208 B2
Microelectronic assemblies having conductive structures with different thicknesses
Brandon C. Marin, Chandler, AZ (US); Andrew James Brown, Phoenix, AZ (US); Rahul Jain, Gilbert, AZ (US); Dilan Seneviratne, Phoenix, AZ (US); Praneeth Kumar Akkinepally, Tempe, AZ (US); and Frank Truong, Gilbert, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 6, 2019, as Appl. No. 16/268,813.
Prior Publication US 2020/0253037 A1, Aug. 6, 2020
Int. Cl. H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H01L 23/498 (2006.01)
CPC H05K 1/0228 (2013.01) [H01L 23/49822 (2013.01); H05K 1/0298 (2013.01); H05K 1/111 (2013.01); H05K 1/115 (2013.01); H05K 1/181 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) doped by an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum;
a first conductive trace having a first thickness in the PID, wherein the first thickness is between 4 um and 143 um; and
a second conductive trace having a second thickness in the PID, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first and second conductive traces have sloped sidewalls.